NAND type flash memories are currently exhibiting amazing growth as a memory for holding non-volatile storage of programs and data. NAND type flash memories include features such as large capacity and also high-speed data transfer. To achieve a large capacity memory, a NAND string structure is utilized that improves the memory cell usage rate by reducing the surface area coupled to the bit lines and memory cells. Large capacity was also attained by micro-fabrication technology and multi-bit storage technology.
These efforts resulted in a memory cell array structure featuring a large number of memory cell coupled to one word line. The NAND type flash memory takes advantage of the features of this structure to improve data transfer efficiency by temporarily storing write data in amounts from several hundred bytes to several kilobytes input from an external section into a buffer inside a chip, and then simultaneously writing that data by a memory cell array operation into a memory cell.
On the other hand, minimal fabrication dimensions are currently approaching the 20 nanometer level where problems are predicted to occur such as a drop in memory cell rewrite durability and faulty memory cell array operation, so that micro-fabrication of NAND type flash memories or in other words fabrication of large capacity memories is reaching its limits.
To break through these limits on micro-fabrication, a phase-change memory has been proposed that utilizes diodes and storage layers comprised of chalcogenide material possessing a structure and operating principle different from NAND type flash memories of the related art and serve as the next generation non-volatile memory.
The storage elements in the phase-change memory cell currently under study utilize chalcogenide material (or phase-change material) including at least antimony (Sb) and tellurium (Te) such as Ge (germanium)-Sb—Te alloy, or Ag (silver)-In (indium)-Sb—Te alloy as the material for the storage layers.
This data rewrite operation in the phase-change memory cell, utilizes Joule heating to change the crystalline state of the storage layer according to the stored data. The data read-out operation on the other hand applies a fixed voltage to the storage layer to distinguish electrical current signals from one another by their resistance values that vary according to the crystalline state.
The structure and operation characteristics of this type of memory cell are described for example in FIG. 1 through FIG. 3 of non-patent document 1 (see IEEE International Solid-State Circuits Conference, Digest of Technical Papers (USA), 2007, pp. 472-473). Moreover, as described in FIG. 7 of International Electron Devices meeting, TECHNICAL DIGEST (USA), 2001, pp. 803-806, the smaller the phase-change region of the storage layer, the less the power required for the write operation (see International Electron Devices meeting, TECHNICAL DIGEST (USA), 2001, pp. 803-806). Phase-change memories are therefore ideal for continuous micro-fabrication and possess good prospects for serving as next generation non-volatile memories.
Achieving phase-change memories having large storage capacity and also a high data transfer rate requires compensating for irregularities in memory cell rewrite properties. Memory chips can store information in the gigabit class where more than one billion memory cells are fabricated so compensating for these irregularities is likely to prove a highly necessary condition.
One widely known method for compensating for irregularities repeatedly performs rewrite while adjusting operation conditions according to the rewrite results. The verifying of rewrite operation results is hereafter in particular called the “Verify read”.
Though repeating the rewrite operation correctly rewrites all of the data, there is the problem on the other hand that the overall time required for the rewrite operation is long.
A method for resolving this problem is known that alternately performs the rewrite operation and the verify read-out operation on a set of two memory cells to in this way conceal the verify readout time (Japanese Unexamined Patent Application Publication No. 2010-113742 and Japanese Unexamined Patent Application Publication No. 2010-129104).